Mechanical strains within a semiconductor device substrate can modulate device performance by, for example, increasing the mobility of the carriers in the semiconductor device. That is, strains within a semiconductor device are known to enhance semiconductor device characteristics. Thus, to improve the characteristics of a semiconductor device, tensile and/or compressive strains are created in the channel of the n-type devices (e.g., NFETs) and/or p-type devices (e.g., PFETs), respectively.
However, the same strain component, for example, tensile strain or compressive strain in a certain direction, may improve the device characteristics of one type of device (i.e., n-type device or p-type device) while discriminatively affecting the characteristics of the other type device. Accordingly, in order to maximize the performance of both NFETs and PFETs within integrated circuit (IC) devices, the strain components should be engineered and applied differently for NFETs and PFETs.
Distinctive processes and different combinations of materials are used to selectively create a strain in a FET. For example, stress memorization techniques (SMT) have been developed to enhance device performance. In SMT, a stress liner encapsulates the NFET device which is then subjected to a high temperature anneal. The high temperature anneal can be upwards of 1100° C. The combination of the amorphizing extension ion implant, a high temperature anneal and stress liner creates stacking fault type defects in the Si of NFET device, near the gate. After anneal, the stress nitride liner is removed by the chemical etch, however, the effect of the stress remains within the NFET device. This effect is known as a stress memorization technique (SMT).
Because the stacking fault can act as a dislocation nucleation site under the influence of high stress and high temperature process conditions, dislocations are prone to appear, mainly on high mobility NFETs. The dislocation defects have been found to coincide with the placement of the stress film on the logic side of the device. This dislocation starts at the end of one stacking fault and, under the influence of high temperature (of about 1100° C.) and stress, moves on a [100] plane towards the gate electrode. It is found that the dislocations end either at the surface of the Si (side wall of Si) or at another stacking fault.
Stacking faults have either an extra plane or a missing plane in 111 stacking direction. The depth and density of stacking faults can vary depending with the process condition. Normally, the more stress during the re-crystallization process, the higher the density of stacking faults generated along the gate. Stacking faults can end in a partial dislocation in single crystal Si or at a Si surface. The partial dislocation are relative immobile; however, as motioned above, the end of fault can act as a source of dislocations under right process conditions, i.e., high temperature and high stress.
Dislocation defects in an otherwise perfect, monolithic crystal structure introduce unwanted and abrupt changes in electrical and optical properties. When a dislocation crosses a junction, it can causes a junction leakage. Dislocation defects are shown in the device of FIG. 1a and FIG. 1b. The dislocation defects can thus impair device performance, e.g., cause high device leakage. In fact, it has been found that leakage can be in the range of about 10-40 μA for an NFET device.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove for high performance devices.